🚀🧠 Calling all tech wizards and engineering superheroes! 💻✨ Are you tired of scrolling through cat memes and dreaming of a job where your brainpower can really shine? Well, dust off your cape because we've got some exciting news! 🦸♂️🦸♀️ 🔍 We're on the lookout for: 🔹 STA Engineer - Whether you can spot a bug from a mile away or you're a pro at untangling those tricky design knots, we want YOU! 🔹 Analog Layout Engineer - If you can turn circuitry into a work of art and have a knack for precision, join us in crafting the future of technology! 🔹 Verification Engineer - Calling all code-crackers and problem-solvers! If you thrive on uncovering the mysteries of digital design, we've got the perfect mission for you! 📍 Locations: Bangalore and Hyderabad - because who says the best jobs are only in Silicon Valley? So, if you've got 4 to 15 years of experience under your utility belt (or even 3 to 8 for our Analog Layout wizards), don't wait! 🚀 Shoot your resume over to mohammed.ismail@smartsocs.com and let's make some magic together! 💫 #SmartSoC #Engineers #Verification #Analog #Layout #STA #JoinTheSmartSide #TechTalentWanted

🚀🧠 Calling all tech wizards and engineering superheroes! 💻✨ Are you tired of scrolling through cat memes and dreaming of a job where your brainpower can really shine? Well, dust off your cape because we've got some exciting news! 🦸♂️🦸♀️ 🔍 We're on the lookout for: 🔹 STA Engineer - Whether you can spot a bug from a mile away or you're a pro at untangling those tricky design knots, we want YOU! 🔹 Analog Layout Engineer - If you can turn circuitry into a work of art and have a knack for precision, join us in crafting the future of technology! 🔹 Verification Engineer - Calling all code-crackers and problem-solvers! If you thrive on uncovering the mysteries of digital design, we've got the perfect mission for you! 📍 Locations: Bangalore and Hyderabad - because who says the best jobs are only in Silicon Valley? So, if you've got 4 to 15 years of experience under your utility belt (or even 3 to 8 for our Analog Layout wizards), don't wait! 🚀 Shoot your resume over to careers@smartsocs.com and let's make some magic together! 💫 #SmartSoC #Engineers #Verification #Analog #Layout #STA #JoinTheSmartSide #TechTalentWanted

We're excited to announce a new opportunity within our Automotive Software team! We are currently looking to hire a Senior/Staff Product Manager who will be primarily responsible for driving Automotive Display and GPU. This role will report directly to me. If you can show industry expertise in Display and GPU technology, we would love to hear from you! Experience in Automotive Software Engineering concepts, JIRA, CodeBeamer will be a bonus. Apply now: https://lnkd.in/gt_-YmRA ID: 3062803 Overview: The successful candidate will help to define and drive automotive-specific multimedia technology (internal IP, external/3P IP, Silicon, Software) product roadmap within Qualcomm’s Automotive business unit. 1) Working with Core Multimedia Technology Product Management teams to leverage existing technology roadmaps as well as aligning and contributing new requirements for future SoCs and shared SW Architectures, specifically: o   Display o   Graphics o   Audio, Video, VIRT I/0, Hypervisor, specific dependencies for Display & Graphics 2) Coordinating primarily display/gpu and related technology features across hardware & software roadmaps for Automotive BU paying consideration to: •   A portfolio which can be leveraged by OEMs, Tier1s and ISVs in the Automotive eco-system •   Ability to work with eco-system partners to provide scalable software offering to customers •   Flexibility within portfolio to respond to changing needs of Digital Cockpit, ADAS, Safety, Automotive Security and Connected Car software requirements  3) Working with core technology product teams and working with leading 3rd party/external technology providers/ecosystem to develop long-term trusted partnerships & solutions to foster roadmap, interface & technology alignment over lengthy automotive product life-cycle: •   Identify & co-ordinate mutual functional-safety requirements with 3rd party visual & display partners Key Responsibilities: •   Collection and Prioritization of Product Requirements, Feature Requests and Software Products to ensure key customer milestones are met in an optimized and efficient manner. •   Generation of the business case associated with any proposed software product •   Working with core multimedia technology management, automotive chipset product management, business development, eco-system management, engineering, program management, customer support and marketing teams to ensure timely and cost-effective delivery of customer SW releases and Proof of Concept & Demo products for internal and external use. •   Working with the Legal, Contracts, Engineering and business support teams to ensure that the necessary in-sourcing and out-bound licensing and SOW agreements and processes are in place to efficiently work with partners, customers and suppliers - including collection and generation of comprehensive documentation of 3rd Party, Proprietary and Open Source Intellectual Property. The preferred location for this position would be in San Diego, CA.

🔍📱 𝐀𝐩𝐩𝐥𝐞’𝐬 𝐔𝐧𝐯𝐞𝐢𝐥𝐢𝐧𝐠 𝐭𝐡𝐞 𝐅𝐮𝐭𝐮𝐫𝐞! 🌐🍏 Did you know? Apple's not just stopping at 𝟓𝐆 - they're already eyeing the realms of 𝟔𝐆 technology! 🚀🔮 In a quest for the next-gen frontier, they're hiring top-notch engineers to shape the future of connectivity. 🛠️🔬 The job listing spills the beans - Apple's on a mission to design and model a 𝟔𝐆 reference architecture! 🎨💡 But hold your horses, the 𝟔𝐆 standard is a futuristic gem, 𝐞𝐱𝐩𝐞𝐜𝐭𝐞𝐝 𝐧𝐨 𝐞𝐚𝐫𝐥𝐢𝐞𝐫 𝐭𝐡𝐚𝐧 𝟐𝟎𝟑𝟎. 🚫 ⏳ The speed race continues, and Apple is geared up for the ride! 🚗💨 Who else is ready to ride the 6G wave? 🏄♂️🍏 #TechRevolution #6GInnovation #futureisnow #6G #speed

#hiring Senior Principal Engineer - Signoff, San Jose, United States, fulltime #jobs #jobseekers #careers #SanJosejobs #Californiajobs #Engineering Apply: https://lnkd.in/g_AhNagM Job Overview: Arm has formed a new group to develop outstanding silicon demonstrators based on Arm's IP compute sub-system solutions and addressing markets such as premium mobile, infrastructure and automotive. Using the latest nodes, e.g. 3nm today, and applying the latest SoC 2.5D and 3D technology, Arm's ambition is to demonstrate industry outstanding performance by architecting, designing, implementing, and fabricating innovative silicon chips. Responsibilities: Your responsibilities will involve developing challenging electrical signoff methodologies. These methodologies will balance accuracy and yield on silicon. The following are the immediate challenges we will be working on as a team: We will develop a Static Timing Analysis flow that is standardized and is usable by all silicon groups within Arm We will work on strengthening our methodologies to analyze static and dynamic IR drop on the SoC. We will release a qualified flow that enable STA with back annotated voltage Electromigration analysis at the SoC level is another key responsibility of this role. Including Local thermal effects as part of electromigration analysis is a key criteria! Soft Error rate is a key concern for Infrastructure and Automotive SoC's. We will develop methodologies to analyze and alleviate the impact of Soft Error rate on SoC's Required Skills and Experience : Experience in developing Signoff methodologies such as Aging, STA, EM IR in advanced process nodes. Experience in collaborating across silicon engineering groups in your organization as well as with EDA vendors Work experience in Physical Implementation and Signoff methodologies Must have worked on methodology development on 5nm or 3nm technologies Strong data analysis skills to fetch data, analyze and provide practical insights "Nice To Have" Skills and Experience : Masters in Electrical Engineering Strong coding skills in Python or R or an equivalent language Strong presentation skills Salary Range From $2 46,925.00 To $ 319,550.00 We value people as individuals and our commitment is to reward people competitively and equitably for the work they do and the skills and experience they bring to Arm. Salary is only one component of Arm's offering. The total reward package will be shared with candidates during the recruitment and selection process. In Return: We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.

#hiring Senior Principal Engineer - Signoff, San Jose, United States, fulltime #jobs #jobseekers #careers #SanJosejobs #Californiajobs #Engineering Apply: https://lnkd.in/g_AhNagM Job Overview: Arm has formed a new group to develop outstanding silicon demonstrators based on Arm's IP compute sub-system solutions and addressing markets such as premium mobile, infrastructure and automotive. Using the latest nodes, e.g. 3nm today, and applying the latest SoC 2.5D and 3D technology, Arm's ambition is to demonstrate industry outstanding performance by architecting, designing, implementing, and fabricating innovative silicon chips. Responsibilities: Your responsibilities will involve developing challenging electrical signoff methodologies. These methodologies will balance accuracy and yield on silicon. The following are the immediate challenges we will be working on as a team: We will develop a Static Timing Analysis flow that is standardized and is usable by all silicon groups within Arm We will work on strengthening our methodologies to analyze static and dynamic IR drop on the SoC. We will release a qualified flow that enable STA with back annotated voltage Electromigration analysis at the SoC level is another key responsibility of this role. Including Local thermal effects as part of electromigration analysis is a key criteria! Soft Error rate is a key concern for Infrastructure and Automotive SoC's. We will develop methodologies to analyze and alleviate the impact of Soft Error rate on SoC's Required Skills and Experience : Experience in developing Signoff methodologies such as Aging, STA, EM IR in advanced process nodes. Experience in collaborating across silicon engineering groups in your organization as well as with EDA vendors Work experience in Physical Implementation and Signoff methodologies Must have worked on methodology development on 5nm or 3nm technologies Strong data analysis skills to fetch data, analyze and provide practical insights "Nice To Have" Skills and Experience : Masters in Electrical Engineering Strong coding skills in Python or R or an equivalent language Strong presentation skills Salary Range From $2 46,925.00 To $ 319,550.00 We value people as individuals and our commitment is to reward people competitively and equitably for the work they do and the skills and experience they bring to Arm. Salary is only one component of Arm's offering. The total reward package will be shared with candidates during the recruitment and selection process. In Return: We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.

#hiring Senior Principal Engineer - Signoff, San Jose, United States, fulltime #jobs #jobseekers #careers #SanJosejobs #Californiajobs Apply: https://lnkd.in/d3JpHyAn Job Overview: Arm has formed a new group to develop outstanding silicon demonstrators based on Arm's IP compute sub-system solutions and addressing markets such as premium mobile, infrastructure and automotive. Using the latest nodes, e.g. 3nm today, and applying the latest SoC 2.5D and 3D technology, Arm's ambition is to demonstrate industry outstanding performance by architecting, designing, implementing, and fabricating innovative silicon chips. Responsibilities: Your responsibilities will involve developing challenging electrical signoff methodologies. These methodologies will balance accuracy and yield on silicon. The following are the immediate challenges we will be working on as a team: We will develop a Static Timing Analysis flow that is standardized and is usable by all silicon groups within Arm We will work on strengthening our methodologies to analyze static and dynamic IR drop on the SoC. We will release a qualified flow that enable STA with back annotated voltage Electromigration analysis at the SoC level is another key responsibility of this role. Including Local thermal effects as part of electromigration analysis is a key criteria! Soft Error rate is a key concern for Infrastructure and Automotive SoC's. We will develop methodologies to analyze and alleviate the impact of Soft Error rate on SoC's Required Skills and Experience : Experience in developing Signoff methodologies such as Aging, STA, EM IR in advanced process nodes. Experience in collaborating across silicon engineering groups in your organization as well as with EDA vendors Work experience in Physical Implementation and Signoff methodologies Must have worked on methodology development on 5nm or 3nm technologies Strong data analysis skills to fetch data, analyze and provide practical insights "Nice To Have" Skills and Experience : Masters in Electrical Engineering Strong coding skills in Python or R or an equivalent language Strong presentation skills Salary Range From $2 46,925.00 To $ 319,550.00 We value people as individuals and our commitment is to reward people competitively and equitably for the work they do and the skills and experience they bring to Arm. Salary is only one component of Arm's offering. The total reward package will be shared with candidates during the recruitment and selection process. In Return: We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.

#hiring Senior Principal Engineer - Signoff, San Jose, United States, fulltime #jobs #jobseekers #careers #SanJosejobs #Californiajobs Apply: https://lnkd.in/d3JpHyAn Job Overview: Arm has formed a new group to develop outstanding silicon demonstrators based on Arm's IP compute sub-system solutions and addressing markets such as premium mobile, infrastructure and automotive. Using the latest nodes, e.g. 3nm today, and applying the latest SoC 2.5D and 3D technology, Arm's ambition is to demonstrate industry outstanding performance by architecting, designing, implementing, and fabricating innovative silicon chips. Responsibilities: Your responsibilities will involve developing challenging electrical signoff methodologies. These methodologies will balance accuracy and yield on silicon. The following are the immediate challenges we will be working on as a team: We will develop a Static Timing Analysis flow that is standardized and is usable by all silicon groups within Arm We will work on strengthening our methodologies to analyze static and dynamic IR drop on the SoC. We will release a qualified flow that enable STA with back annotated voltage Electromigration analysis at the SoC level is another key responsibility of this role. Including Local thermal effects as part of electromigration analysis is a key criteria! Soft Error rate is a key concern for Infrastructure and Automotive SoC's. We will develop methodologies to analyze and alleviate the impact of Soft Error rate on SoC's Required Skills and Experience : Experience in developing Signoff methodologies such as Aging, STA, EM IR in advanced process nodes. Experience in collaborating across silicon engineering groups in your organization as well as with EDA vendors Work experience in Physical Implementation and Signoff methodologies Must have worked on methodology development on 5nm or 3nm technologies Strong data analysis skills to fetch data, analyze and provide practical insights "Nice To Have" Skills and Experience : Masters in Electrical Engineering Strong coding skills in Python or R or an equivalent language Strong presentation skills Salary Range From $2 46,925.00 To $ 319,550.00 We value people as individuals and our commitment is to reward people competitively and equitably for the work they do and the skills and experience they bring to Arm. Salary is only one component of Arm's offering. The total reward package will be shared with candidates during the recruitment and selection process. In Return: We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.

#hiring Senior Principal Engineer - Signoff, San Jose, United States, fulltime #jobs #jobseekers #careers #SanJosejobs #Californiajobs #Engineering Apply: https://lnkd.in/grFscY2V Job Overview: Arm has formed a new group to develop outstanding silicon demonstrators based on Arm's IP compute sub-system solutions and addressing markets such as premium mobile, infrastructure and automotive. Using the latest nodes, e.g. 3nm today, and applying the latest SoC 2.5D and 3D technology, Arm's ambition is to demonstrate industry outstanding performance by architecting, designing, implementing, and fabricating innovative silicon chips. Responsibilities: Your responsibilities will involve developing challenging electrical signoff methodologies. These methodologies will balance accuracy and yield on silicon. The following are the immediate challenges we will be working on as a team: We will develop a Static Timing Analysis flow that is standardized and is usable by all silicon groups within Arm We will work on strengthening our methodologies to analyze static and dynamic IR drop on the SoC. We will release a qualified flow that enable STA with back annotated voltage Electromigration analysis at the SoC level is another key responsibility of this role. Including Local thermal effects as part of electromigration analysis is a key criteria! Soft Error rate is a key concern for Infrastructure and Automotive SoC's. We will develop methodologies to analyze and alleviate the impact of Soft Error rate on SoC's Required Skills and Experience : Experience in developing Signoff methodologies such as Aging, STA, EM IR in advanced process nodes. Experience in collaborating across silicon engineering groups in your organization as well as with EDA vendors Work experience in Physical Implementation and Signoff methodologies Must have worked on methodology development on 5nm or 3nm technologies Strong data analysis skills to fetch data, analyze and provide practical insights "Nice To Have" Skills and Experience : Masters in Electrical Engineering Strong coding skills in Python or R or an equivalent language Strong presentation skills Salary Range From $2 46,925.00 To $ 319,550.00 We value people as individuals and our commitment is to reward people competitively and equitably for the work they do and the skills and experience they bring to Arm. Salary is only one component of Arm's offering. The total reward package will be shared with candidates during the recruitment and selection process. In Return: We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.

#hiring Senior Principal Engineer - Signoff, San Jose, United States, fulltime #jobs #jobseekers #careers #SanJosejobs #Californiajobs #Engineering Apply: https://lnkd.in/grFscY2V Job Overview: Arm has formed a new group to develop outstanding silicon demonstrators based on Arm's IP compute sub-system solutions and addressing markets such as premium mobile, infrastructure and automotive. Using the latest nodes, e.g. 3nm today, and applying the latest SoC 2.5D and 3D technology, Arm's ambition is to demonstrate industry outstanding performance by architecting, designing, implementing, and fabricating innovative silicon chips. Responsibilities: Your responsibilities will involve developing challenging electrical signoff methodologies. These methodologies will balance accuracy and yield on silicon. The following are the immediate challenges we will be working on as a team: We will develop a Static Timing Analysis flow that is standardized and is usable by all silicon groups within Arm We will work on strengthening our methodologies to analyze static and dynamic IR drop on the SoC. We will release a qualified flow that enable STA with back annotated voltage Electromigration analysis at the SoC level is another key responsibility of this role. Including Local thermal effects as part of electromigration analysis is a key criteria! Soft Error rate is a key concern for Infrastructure and Automotive SoC's. We will develop methodologies to analyze and alleviate the impact of Soft Error rate on SoC's Required Skills and Experience : Experience in developing Signoff methodologies such as Aging, STA, EM IR in advanced process nodes. Experience in collaborating across silicon engineering groups in your organization as well as with EDA vendors Work experience in Physical Implementation and Signoff methodologies Must have worked on methodology development on 5nm or 3nm technologies Strong data analysis skills to fetch data, analyze and provide practical insights "Nice To Have" Skills and Experience : Masters in Electrical Engineering Strong coding skills in Python or R or an equivalent language Strong presentation skills Salary Range From $2 46,925.00 To $ 319,550.00 We value people as individuals and our commitment is to reward people competitively and equitably for the work they do and the skills and experience they bring to Arm. Salary is only one component of Arm's offering. The total reward package will be shared with candidates during the recruitment and selection process. In Return: We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.