Recent studies of Lim et al. have shown that channel engineering can effectively be used to globally improve the device noise performance. This happens because the doping profile can strongly impact the correlation between the drain and induced gate noise. In this brief, we will use the theory developed in the recent works of Roy et al. to provide a physical understanding and insight on the behavior of the gate-drain correlation coefficient, which will be very useful for understanding the mechanism by which the doping profile impacts the RF noise performance of a MOSFET.

In this paper, for the first time, we present a detailed RF experimental and simulation study of a 3-D multichannel SOI MOSFET (MCFET). Being different from the conventional planar technology, the MCFET features a total of three self-aligned TiN/HfO 2 gate stacks fabricated on top of each other, allowing current to flow through the three undoped ultrathinned silicon bodies (UTBs). In other words, the operation of the MCFET is theoretically based on two UTB double-gate SOIs and a single-gate UTB fully depleted SOI (FDSOI) at the bottom. Using on-wafer S-parameters, the RF/analog figures-of-merit of an MCFET with a gate length of 50 nm are extracted and discussed. Thanks to the enormous transconductance (g m ) and very low output conductance, the RF/analog performances of MCFET-voltage gain (A VI ) and early voltage (V EA ) are superior compared with that of the single-gate UTB-FDSOI. However, these advantages diminish in terms of transition frequency (f T ), due to the large total input gate capacitances (C GG ). This inspires the introduction of spacer engineering in MCFET, aiming at improving both C GG and f T . The sensitivity of the spacer length to the RF/analog performances is experimentally analyzed, and the performance optimization is validated using ac simulation. This paper concludes that optimized MCFETs are a serious contender to the mainstream MOSFETs including FinFETs for realizing future low-power analog applications.

This paper presents a detailed RF study for source/drain Schottky-barrier (SB) MOSFETs. Using on-wafer S-parameters, high-frequency (HF) figures-of-merit (FoMs) and small-signal equivalent circuits (SSEC) are first extracted and discussed for a 120-nm-gate-length SB MOSFET. Then, using ac simulations, HF FoM's sensitivity along SB height and underlap length variations are subsequently presented. The whole study provides, for SB MOSFETs, a deep understanding of key acelement (transconductances and capacitances) behavior as well as process-parameter optimization to achieve the best HF FoMs.

In this paper, measured RF noise performance of graded-channel metal-oxide-semiconductor (MOS) transistors (GCMOS-also named laterally asymmetric channel transistors) shows impressive reduction in minimum noise figure (N F min ) as compared to classical MOSFET transistors (with the same gate length L g = 0.5 μm). The reason is proven to be because of the higher noise correlation coefficient (C). GCMOS also shows lower sensitivity to extrinsic thermal noise as compared to classical MOSFET. Moreover, it is demonstrated that the use of 0.5-μm-gate-length GCMOS gives a competitive RF noise performance as compared to 0.25-μm-gate-length classical nMOS transistors.

Recent studies of Lim et al. have shown that channel engineering can effectively be used to globally improve the device noise performance. This happens because the doping profile can strongly impact the correlation between the drain and induced gate noise. In this brief, we will use the theory developed in the recent works of Roy et al. to provide a physical understanding and insight on the behavior of the gate-drain correlation coefficient, which will be very useful for understanding the mechanism by which the doping profile impacts the RF noise performance of a MOSFET.